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Add support for read_aiger -wideports

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This commit is contained in:
Eddie Hung 2019-02-12 12:58:10 -08:00
parent 06ba81d41f
commit e9df9a466a
2 changed files with 15 additions and 6 deletions
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18
frontends/aiger/aigerparse.cc
View file

@ -33,8 +33,8 @@ YOSYS_NAMESPACE_BEGIN
#define log_debug log #define log_debug log
AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename) AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
: design(design), f(f), clk_name(clk_name), map_filename(map_filename) : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
{ {
module = new RTLIL::Module; module = new RTLIL::Module;
module->name = module_name; module->name = module_name;
@ -223,7 +223,6 @@ void AigerReader::parse_xaiger()
log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
} }
bool wideports = true;
dict<RTLIL::IdString, int> wideports_cache; dict<RTLIL::IdString, int> wideports_cache;
if (!map_filename.empty()) { if (!map_filename.empty()) {
@ -284,7 +283,7 @@ void AigerReader::parse_xaiger()
wire->port_output = other_wire->port_output; wire->port_output = other_wire->port_output;
other_wire->port_input = false; other_wire->port_input = false;
other_wire->port_output = false; other_wire->port_output = false;
if (wire->port_input) if (wire->port_output)
module->connect(other_wire, SigSpec(wire, i)); module->connect(other_wire, SigSpec(wire, i));
else else
module->connect(SigSpec(wire, i), other_wire); module->connect(SigSpec(wire, i), other_wire);
@ -566,6 +565,10 @@ struct AigerFrontend : public Frontend {
log(" -map <filename>\n"); log(" -map <filename>\n");
log(" read file with port and latch symbols\n"); log(" read file with port and latch symbols\n");
log("\n"); log("\n");
log(" -wideports\n");
log(" Merge ports that match the pattern 'name[int]' into a single\n");
log(" multi-bit port 'name'.\n");
log("\n");
} }
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
@ -574,6 +577,7 @@ struct AigerFrontend : public Frontend {
RTLIL::IdString clk_name = "\\clk"; RTLIL::IdString clk_name = "\\clk";
RTLIL::IdString module_name; RTLIL::IdString module_name;
std::string map_filename; std::string map_filename;
bool wideports = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
@ -590,6 +594,10 @@ struct AigerFrontend : public Frontend {
map_filename = args[++argidx]; map_filename = args[++argidx];
continue; continue;
} }
if (arg == "-wideports") {
wideports = true;
continue;
}
break; break;
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
@ -602,7 +610,7 @@ struct AigerFrontend : public Frontend {
#endif #endif
} }
AigerReader reader(design, *f, module_name, clk_name, map_filename); AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
reader.parse_aiger(); reader.parse_aiger();
} }
} AigerFrontend; } AigerFrontend;

3
frontends/aiger/aigerparse.h
View file

@ -31,6 +31,7 @@ struct AigerReader
RTLIL::IdString clk_name; RTLIL::IdString clk_name;
RTLIL::Module *module; RTLIL::Module *module;
std::string map_filename; std::string map_filename;
bool wideports;
unsigned M, I, L, O, A; unsigned M, I, L, O, A;
unsigned B, C, J, F; // Optional in AIGER 1.9 unsigned B, C, J, F; // Optional in AIGER 1.9
@ -40,7 +41,7 @@ struct AigerReader
std::vector<RTLIL::Wire*> latches; std::vector<RTLIL::Wire*> latches;
std::vector<RTLIL::Wire*> outputs; std::vector<RTLIL::Wire*> outputs;
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename); AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger(); void parse_aiger();
void parse_xaiger(); void parse_xaiger();
void parse_aiger_ascii(bool create_and); void parse_aiger_ascii(bool create_and);