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Fixed handling of boolean attributes (backends)

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This commit is contained in:
Clifford Wolf 2013-10-24 11:27:30 +02:00
parent 23cf23418c
commit e9dede01ca
6 changed files with 10 additions and 10 deletions
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6
backends/autotest/autotest.cc
View file

@ -109,7 +109,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
} else if (wire->port_input) { } else if (wire->port_input) {
count_ports++; count_ports++;
bool is_clksignal = wire->attributes.count("\\gentb_clock") > 0; bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++) for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++)
for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) { for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) {
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
@ -120,11 +120,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
is_clksignal = true; is_clksignal = true;
} }
} }
if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
signal_clk[idy("sig", mod->name, wire->name)] = wire->width; signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
} else { } else {
signal_in[idy("sig", mod->name, wire->name)] = wire->width; signal_in[idy("sig", mod->name, wire->name)] = wire->width;
if (wire->attributes.count("\\gentb_constant") > 0) if (wire->get_bool_attribute("\\gentb_constant"))
signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string(); signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
} }
fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());

2
backends/blif/blif.cc
View file

@ -298,7 +298,7 @@ struct BlifBackend : public Backend {
for (auto module_it : design->modules) for (auto module_it : design->modules)
{ {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
if ((module->attributes.count("\\placeholder") > 0) > 0) if ((module->get_bool_attribute("\\placeholder")) > 0)
continue; continue;
if (module->processes.size() != 0) if (module->processes.size() != 0)

6
backends/edif/edif.cc
View file

@ -118,7 +118,7 @@ struct EdifBackend : public Backend {
for (auto module_it : design->modules) for (auto module_it : design->modules)
{ {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
if ((module->attributes.count("\\placeholder") > 0) > 0) if (module->get_bool_attribute("\\placeholder"))
continue; continue;
if (top_module_name.empty()) if (top_module_name.empty())
@ -132,7 +132,7 @@ struct EdifBackend : public Backend {
for (auto cell_it : module->cells) for (auto cell_it : module->cells)
{ {
RTLIL::Cell *cell = cell_it.second; RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->attributes.count("\\placeholder")) { if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
lib_cell_ports[cell->type]; lib_cell_ports[cell->type];
for (auto p : cell->connections) { for (auto p : cell->connections) {
if (p.second.width > 1) if (p.second.width > 1)
@ -200,7 +200,7 @@ struct EdifBackend : public Backend {
for (auto module_it : design->modules) for (auto module_it : design->modules)
{ {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
if ((module->attributes.count("\\placeholder") > 0) > 0) if (module->get_bool_attribute("\\placeholder"))
continue; continue;
SigMap sigmap(module); SigMap sigmap(module);

2
backends/intersynth/intersynth.cc
View file

@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
SigMap sigmap(module); SigMap sigmap(module);
if (module->attributes.count("\\placeholder") > 0) if (module->get_bool_attribute("\\placeholder"))
continue; continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
continue; continue;

2
backends/spice/spice.cc
View file

@ -181,7 +181,7 @@ struct SpiceBackend : public Backend {
for (auto module_it : design->modules) for (auto module_it : design->modules)
{ {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
if ((module->attributes.count("\\placeholder") > 0) > 0) if (module->get_bool_attribute("\\placeholder"))
continue; continue;
if (module->processes.size() != 0) if (module->processes.size() != 0)

2
backends/verilog/verilog_backend.cc
View file

@ -957,7 +957,7 @@ struct VerilogBackend : public Backend {
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) { for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if ((it->second->attributes.count("\\placeholder") > 0) != placeholders) if (it->second->get_bool_attribute("\\placeholder") != placeholders)
continue; continue;
if (selected && !design->selected_whole_module(it->first)) { if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first)) if (design->selected_module(it->first))