mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Fixed handling of boolean attributes (backends)

Browse source
This commit is contained in:
Clifford Wolf 2013-10-24 11:27:30 +02:00
parent 23cf23418c
commit e9dede01ca
6 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/verilog/verilog_backend.cc
View file

@ -957,7 +957,7 @@ struct VerilogBackend : public Backend {
extra_args(f, filename, args, argidx);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if ((it->second->attributes.count("\\placeholder") > 0) != placeholders)
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
continue;
if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first))