mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Indenting fixes in gowin sim cell lib

Browse source
This commit is contained in:
Clifford Wolf 2016-11-08 18:54:00 +01:00
parent 97ac77513f
commit e9d73d2ee0
1 changed files with 28 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

12
techlibs/gowin/cells_sim.v
View file

@ -25,12 +25,16 @@ module LUT4(output F, input I0, I1, I2, I3);
endmodule
module DFF (output reg Q, input CLK, D);
always @(posedge C)
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK)
Q <= D;
endmodule
module DFFN (output reg Q, input CLK, D);
always @(negedge C)
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge CLK)
Q <= D;
endmodule
@ -49,3 +53,7 @@ endmodule
module OBUF(output O, input I);
assign O = I;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule