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https://github.com/YosysHQ/yosys
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Added "equiv_simple -undef"
This commit is contained in:
Clifford Wolf
parent
f80f5b721d
commit
e9cfc4a453
2 changed files with 61 additions and 17 deletions
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@ -103,6 +103,20 @@ struct SatGen
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return importSigSpecWorker(bit, pf, false, false).front();
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}
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int importDefSigBit(RTLIL::SigBit bit, int timestep = -1)
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{
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log_assert(timestep != 0);
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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return importSigSpecWorker(bit, pf, false, true).front();
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}
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int importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)
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{
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log_assert(timestep != 0);
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std::string pf = "undef:" + prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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return importSigSpecWorker(bit, pf, true, false).front();
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}
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bool importedSigBit(RTLIL::SigBit bit, int timestep = -1)
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{
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log_assert(timestep != 0);
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@ -36,21 +36,22 @@ struct EquivSimpleWorker
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int max_seq;
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bool verbose;
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EquivSimpleWorker(Cell *equiv_cell, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose) :
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EquivSimpleWorker(Cell *equiv_cell, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose, bool model_undef) :
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module(equiv_cell->module), equiv_cell(equiv_cell), sigmap(sigmap),
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bit2driver(bit2driver), satgen(&ez, &sigmap), max_seq(max_seq), verbose(verbose)
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{
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satgen.model_undef = model_undef;
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}
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, Cell *cell)
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bool find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, pool<SigBit> *input_bits, Cell *cell)
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{
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if (cells_cone.count(cell))
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return;
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return false;
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cells_cone.insert(cell);
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if (cells_stop.count(cell))
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return;
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return true;
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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@ -59,24 +60,28 @@ struct EquivSimpleWorker
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if (!conn.first.in("\\CLK", "\\C"))
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next_seed.insert(bit);
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} else
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, bit);
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
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}
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return false;
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}
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, SigBit bit)
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, pool<SigBit> *input_bits, SigBit bit)
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{
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if (bits_cone.count(bit))
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return;
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bits_cone.insert(bit);
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if (bits_stop.count(bit))
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if (bits_stop.count(bit)) {
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if (input_bits != nullptr) input_bits->insert(bit);
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return;
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}
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if (!bit2driver.count(bit))
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return;
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, bit2driver.at(bit));
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if (find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit2driver.at(bit)))
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if (input_bits != nullptr) input_bits->insert(bit);
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}
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bool run()
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@ -84,9 +89,21 @@ struct EquivSimpleWorker
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importSigBit(bit_b, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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if (satgen.model_undef)
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{
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importDefSigBit(bit_b, max_seq+1);
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int ez_undef_a = satgen.importUndefSigBit(bit_a, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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ez.assume(ez.NOT(ez_undef_a));
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}
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else
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{
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importSigBit(bit_b, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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}
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pool<SigBit> seed_a = { bit_a };
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pool<SigBit> seed_b = { bit_b };
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@ -110,22 +127,23 @@ struct EquivSimpleWorker
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pool<SigBit> next_seed_a, next_seed_b;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, bit_a);
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find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
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next_seed_a.clear();
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, bit_b);
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find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
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next_seed_b.clear();
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pool<Cell*> short_cells_cone_a, short_cells_cone_b;
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pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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pool<SigBit> input_bits;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, bit_a);
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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next_seed_a.swap(seed_a);
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, bit_b);
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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next_seed_b.swap(seed_b);
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pool<Cell*> problem_cells;
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@ -141,6 +159,11 @@ struct EquivSimpleWorker
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if (!satgen.importCell(cell, step+1))
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log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
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if (satgen.model_undef) {
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for (auto bit : input_bits)
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ez.assume(ez.NOT(satgen.importUndefSigBit(bit, step+1)));
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}
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if (verbose)
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log(" Problem size at t=%d: %d literals, %d clauses\n", step, ez.numCnfVariables(), ez.numCnfClauses());
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@ -209,13 +232,16 @@ struct EquivSimplePass : public Pass {
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log(" -v\n");
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log(" verbose output\n");
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log("\n");
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log(" -undef\n");
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log(" enable modelling of undef states\n");
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log("\n");
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log(" -seq <N>\n");
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log(" the max. number of time steps to be considered (default = 1)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool verbose = false;
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bool verbose = false, model_undef = false;
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int success_counter = 0;
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int max_seq = 1;
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@ -227,6 +253,10 @@ struct EquivSimplePass : public Pass {
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verbose = true;
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continue;
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}
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if (args[argidx] == "-undef") {
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model_undef = true;
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continue;
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}
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if (args[argidx] == "-seq" && argidx+1 < args.size()) {
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max_seq = atoi(args[++argidx].c_str());
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continue;
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@ -266,7 +296,7 @@ struct EquivSimplePass : public Pass {
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std::sort(unproven_equiv_cells.begin(), unproven_equiv_cells.end());
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for (auto it : unproven_equiv_cells) {
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EquivSimpleWorker worker(it.second, sigmap, bit2driver, max_seq, verbose);
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EquivSimpleWorker worker(it.second, sigmap, bit2driver, max_seq, verbose, model_undef);
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if (worker.run())
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success_counter++;
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}
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