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Fix formatting for msys2 mingw build using GetSize

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This commit is contained in:
Miodrag Milanovic 2019-07-31 11:49:48 +02:00 • committed by Clifford Wolf
parent 82a2972068
commit e9c5f1b346
8 changed files with 20 additions and 17 deletions
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8
passes/opt/opt_lut.cc
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@ -81,7 +81,7 @@ struct OptLutWorker
}
}
log("Number of LUTs: %8zu\n", luts.size());
log("Number of LUTs: %8d\n", GetSize(luts));
for (int arity = 1; arity <= max_arity; arity++)
{
if (arity_counts[arity])
@ -353,14 +353,14 @@ struct OptLutWorker
int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
if (lutA_dlogic_inputs.size())
log(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
log(" Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
else
log(" Cell A is a %d-LUT. ", lutA_arity);
if (lutB_dlogic_inputs.size())
log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
log("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
else
log("Cell B is a %d-LUT.\n", lutB_arity);
log(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
log(" Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
int combine_mask = 0;

2
passes/opt/rmports.cc
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@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
wire->port_output = false;
wire->port_id = 0;
}
log("Removed %zu unused ports.\n", unused_ports.size());
log("Removed %d unused ports.\n", GetSize(unused_ports));
// Re-number all of the wires that DO have ports still on them
for(size_t i=0; i<module->ports.size(); i++)