mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

cxxrtl: add missing parts of commit 281c9685.

Browse source
This commit is contained in:
whitequark 2020-05-26 06:00:40 +00:00
parent 59b355fb85
commit e9c07e2bda
1 changed files with 3 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

8
backends/cxxrtl/cxxrtl.cc
View file

@ -513,7 +513,6 @@ struct CxxrtlWorker {
bool elide_public = false; bool elide_public = false;
bool localize_internal = false; bool localize_internal = false;
bool localize_public = false; bool localize_public = false;
bool run_opt_clean_purge = false;
bool run_proc_flatten = false; bool run_proc_flatten = false;
bool max_opt_level = false; bool max_opt_level = false;
@ -2046,7 +2045,7 @@ struct CxxrtlWorker {
} }
if (has_feedback_arcs || has_buffered_wires) { if (has_feedback_arcs || has_buffered_wires) {
// Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
// by optimizing the design, if after `opt_clean -purge` there are any feedback wires remaining, it is very // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
// likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message. // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
const char *why_pessimistic = nullptr; const char *why_pessimistic = nullptr;
if (has_feedback_arcs) if (has_feedback_arcs)
@ -2106,15 +2105,13 @@ struct CxxrtlWorker {
if (has_sync_init || has_packed_mem) if (has_sync_init || has_packed_mem)
check_design(design, has_sync_init, has_packed_mem); check_design(design, has_sync_init, has_packed_mem);
log_assert(!(has_sync_init || has_packed_mem)); log_assert(!(has_sync_init || has_packed_mem));
if (run_opt_clean_purge)
Pass::call(design, "opt_clean -purge");
log_pop(); log_pop();
analyze_design(design); analyze_design(design);
} }
}; };
struct CxxrtlBackend : public Backend { struct CxxrtlBackend : public Backend {
static const int DEFAULT_OPT_LEVEL = 6; static const int DEFAULT_OPT_LEVEL = 5;
CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { } CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
@ -2340,6 +2337,7 @@ struct CxxrtlBackend : public Backend {
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
switch (opt_level) { switch (opt_level) {
// the highest level here must match DEFAULT_OPT_LEVEL
case 5: case 5:
worker.max_opt_level = true; worker.max_opt_level = true;
worker.run_proc_flatten = true; worker.run_proc_flatten = true;