From e9aedf505c5f4260c14b699ba3ab584d43bd72f0 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 9 Oct 2025 02:08:20 +0200
Subject: [PATCH] chtype: replace publish pass with chtype -publish_icells

---
 passes/cmds/Makefile.inc        |  1 -
 passes/cmds/chtype.cc           | 32 ++++++++++++++++++++++++
 passes/cmds/publish.cc          | 43 ---------------------------------
 tests/techmap/techmap_chtype.ys | 16 ++++++++++++
 4 files changed, 48 insertions(+), 44 deletions(-)
 delete mode 100644 passes/cmds/publish.cc

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index f4c4db2f8..9bf615a7e 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -57,4 +57,3 @@ OBJS += passes/cmds/abstract.o
 OBJS += passes/cmds/test_select.o
 OBJS += passes/cmds/timeest.o
 OBJS += passes/cmds/linecoverage.o
-OBJS += passes/cmds/publish.o
diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc
index 6f9ca9a45..eb194f3e3 100644
--- a/passes/cmds/chtype.cc
+++ b/passes/cmds/chtype.cc
@@ -22,6 +22,27 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+static void publish(RTLIL::IdString& id) {
+	if (id.begins_with("$")) {
+		log_debug("publishing %s\n", id.c_str());
+		id = "\\" + id.str();
+		log_debug("published %s\n", id.c_str());
+	}
+}
+
+static void publish_design(RTLIL::Design* design) {
+	auto saved_modules = design->modules_;
+	design->modules_.clear();
+	for (auto& [name, mod] : saved_modules) {
+		publish(mod->name);
+		design->modules_[mod->name] = mod;
+		for (auto* cell : mod->cells()) {
+			publish(cell->type);
+		}
+	}
+}
+
+
 struct ChtypePass : public Pass {
 	ChtypePass() : Pass("chtype", "change type of cells in the design") { }
 	void help() override
@@ -38,12 +59,16 @@ struct ChtypePass : public Pass {
 		log("    -map <old_type> <new_type>\n");
 		log("        change cells types that match <old_type> to <new_type>\n");
 		log("\n");
+		log("    -publish_icells\n");
+		log("        change internal cells types to public types\n");
+		log("\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		IdString set_type;
 		dict<IdString, IdString> map_types;
+		bool publish_mode = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -58,10 +83,17 @@ struct ChtypePass : public Pass {
 				map_types[old_type] = new_type;
 				continue;
 			}
+			if (args[argidx] == "-publish_icells") {
+				publish_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		if (publish_mode)
+			publish_design(design);
+
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
diff --git a/passes/cmds/publish.cc b/passes/cmds/publish.cc
deleted file mode 100644
index 45a3ef5de..000000000
--- a/passes/cmds/publish.cc
+++ /dev/null
@@ -1,43 +0,0 @@
-#include "kernel/register.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct PublishPass : public Pass {
-private:
-	static void publish(RTLIL::IdString& id) {
-		if (id.begins_with("$")) {
-			log_debug("publishing %s\n", id.c_str());
-			id = "\\" + id.str();
-			log_debug("published %s\n", id.c_str());
-		}
-	}
-public:
-	PublishPass() : Pass("publish", "publish private cell types") { }
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    publish\n");
-		log("Makes all module names and cell types public by prefixing\n");
-		log("%% with \\.\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		log_header(design, "Executing PUBLISH pass. (make cell types public)\n");
-		extra_args(args, 1, design);
-		auto saved_modules = design->modules_;
-		design->modules_.clear();
-		for (auto& [name, mod] : saved_modules) {
-			publish(mod->name);
-			design->modules_[mod->name] = mod;
-			for (auto* cell : mod->cells()) {
-				publish(cell->type);
-			}
-		}
-	}
-} PublishPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/tests/techmap/techmap_chtype.ys b/tests/techmap/techmap_chtype.ys
index 7c3398420..0c759e448 100644
--- a/tests/techmap/techmap_chtype.ys
+++ b/tests/techmap/techmap_chtype.ys
@@ -31,3 +31,19 @@ opt
 techmap -map %techmap
 
 select -assert-count 1 t:LCU_8
+
+design -reset
+read_verilog <<EOT
+module top(input A, input B, output Y);
+assign Y = A ^ B;
+endmodule
+EOT
+
+# We can only test that the option doesn't crash
+# See https://github.com/YosysHQ/yosys/issues/5414
+
+# select -assert-count 1 t:$xor
+# select -assert-count 0 t:\$xor
+chtype -publish_icells
+# select -assert-count 0 t:$xor
+# select -assert-count 1 t:\$xor