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Merge pull request #1213 from YosysHQ/eddie/wreduce_add
wreduce/opt_expr: improve width reduction for $add and $sub cells
This commit is contained in:
Clifford Wolf
GitHub
commit
e9a756aa7a
5 changed files with 226 additions and 3 deletions
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@ -788,6 +788,7 @@ public:
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RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
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RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
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RTLIL::SigSpec extract(int offset, int length = 1) const;
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RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
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void append(const RTLIL::SigSpec &signal);
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void append_bit(const RTLIL::SigBit &bit);
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@ -834,6 +835,7 @@ public:
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operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
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unsigned int hash() const { if (!hash_) updhash(); return hash_; };
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@ -641,6 +641,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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did_something = true;
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}
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}
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if (cell->type.in("$add", "$sub")) {
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RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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bool sub = cell->type == "$sub";
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_a[i]);
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else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_b[i]);
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else
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break;
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}
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if (i > 0) {
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cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
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cell->setPort("\\A", sig_a.extract_end(i));
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cell->setPort("\\B", sig_b.extract_end(i));
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cell->setPort("\\Y", sig_y.extract_end(i));
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cell->fixup_parameters();
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did_something = true;
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}
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}
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}
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if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
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@ -342,9 +342,9 @@ struct WreduceWorker
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}
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}
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if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor"))
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if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub"))
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{
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub";
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int a_size = 0, b_size = 0;
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if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
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@ -352,7 +352,7 @@ struct WreduceWorker
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int max_y_size = max(a_size, b_size);
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if (cell->type == "$add")
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if (cell->type.in("$add", "$sub"))
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max_y_size++;
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if (cell->type == "$mul")
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148
tests/various/opt_expr.ys
Normal file
148
tests/various/opt_expr.ys
Normal file
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@ -0,0 +1,148 @@
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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48
tests/various/wreduce.ys
Normal file
48
tests/various/wreduce.ys
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@ -0,0 +1,48 @@
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read_verilog <<EOT
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module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (j >> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (j >>> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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dump
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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