mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

write_verilog: dump $mem cell attributes.

Browse source 
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
This commit is contained in:
whitequark 2020-02-06 16:22:22 +00:00
parent d44848328b
commit e95a8ba763
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
backends/verilog/verilog_backend.cc
View file

@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// initial begin
// memid[0] = ...
// end
dump_attributes(f, indent.c_str(), cell->attributes);
f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
if (use_init)
{