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fsm_extract: Initialize celltypes with full design.

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Fixes #1781.
This commit is contained in:
Marcin Kościelnicki 2020-03-18 20:58:36 +01:00 committed by Marcelina Kościelnicka
parent d46259becd
commit e91368a5f4
2 changed files with 34 additions and 5 deletions
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6
passes/fsm/fsm_extract.cc
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@ -422,11 +422,7 @@ struct FsmExtractPass : public Pass {
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design); extra_args(args, 1, design);
CellTypes ct; CellTypes ct(design);
ct.setup_internals();
ct.setup_internals_mem();
ct.setup_stdcells();
ct.setup_stdcells_mem();
for (auto &mod_it : design->modules_) for (auto &mod_it : design->modules_)
{ {

33
tests/various/bug1781.ys Normal file
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@ -0,0 +1,33 @@
read_verilog <<EOT
module top(input clk, input rst);
reg [1:0] state;
always @(posedge clk, posedge rst) begin
if (rst)
state <= 0;
else
case (state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b10: state <= 2'b00;
endcase
end
sub sub_i(.i(state == 0));
endmodule
(* blackbox, keep *)
module sub(input i);
endmodule
EOT
proc
fsm
# Make sure there is a driver
select -assert-any t:sub %ci %a w:* %i %ci c:* %i