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peepopt.muldiv: Add a signedness check.

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Fixes #2318.
This commit is contained in:
Marcelina Kościelnicka 2020-08-04 16:30:24 +02:00
parent c39ebe6ae0
commit e89cc9c02f
2 changed files with 16 additions and 1 deletions
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12
tests/opt/bug2318.ys Normal file
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read_verilog <<EOT
module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
wire [7:0] P = A * B;
wire signed [7:0] SP = P;
wire signed [3:0] SB = B;
assign Y = SP / SB;
endmodule
EOT
equiv_opt -assert peepopt