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Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.
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6 changed files with 5 additions and 3 deletions
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@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("map_luts"))
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{
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run("sort");
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if (nowidelut && abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v");
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run("abc9 -maxlut 4 -W 500");
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