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Cleanup

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This commit is contained in:
Eddie Hung 2019-08-09 15:47:40 -07:00
parent 0b5b56c1ec
commit e83f231927
2 changed files with 18 additions and 18 deletions
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20
passes/pmgen/xilinx_dsp.pmg
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@ -9,11 +9,11 @@ match dsp
endmatch
match ffA
if param(dsp, \AREG).as_int() == 0
if !port(dsp, \A).remove_const().empty()
select ffA->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffA, \CLK_POLARITY).as_bool()
filter param(dsp, \AREG).as_int() == 0
filter !port(dsp, \A).remove_const().empty()
filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
optional
endmatch
@ -24,11 +24,11 @@ code clock
endcode
match ffB
if param(dsp, \BREG).as_int() == 0
if !port(dsp, \B).remove_const().empty()
select ffB->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffB, \CLK_POLARITY).as_bool()
filter param(dsp, \BREG).as_int() == 0
filter !port(dsp, \B).remove_const().empty()
filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
optional
endmatch
@ -51,9 +51,9 @@ endcode
match addA
select addA->type.in($add)
select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
select nusers(port(addA, \A)) == 2
index <int> nusers(port(addA, \A)) === 2
//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int())
filter GetSize(sigP) >= param(addA, \A_WIDTH).as_int()
filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP)
filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int())
optional
endmatch
@ -62,9 +62,9 @@ match addB
if !addA
select addB->type.in($add, $sub)
select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
select nusers(port(addB, \B)) == 2
index <int> nusers(port(addB, \B)) === 2
//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
filter GetSize(sigP) >= param(addB, \B_WIDTH).as_int()
filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int())
optional
endmatch
@ -110,12 +110,12 @@ code sigPused
endcode
match ffP
if param(dsp, \PREG).as_int() == 0
if !sigPused.empty()
select ffP->type.in($dff)
select nusers(port(ffP, \D)) == 2
index <int> nusers(port(ffP, \D)) === 2
// DSP48E1 does not support clock inversion
select param(ffP, \CLK_POLARITY).as_bool()
filter param(dsp, \PREG).as_int() == 0
filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
optional