verilog: use derived module info to elaborate cell connections

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change

tests/simple/memwr_port_connection.sv

@@ -0,0 +1,13 @@
+module producer(
+    output logic [3:0] out
+);
+    assign out = 4'hA;
+endmodule
+
+module top(
+    output logic [3:0] out
+);
+    logic [3:0] v[0:0];
+    producer p(v[0]);
+    assign out = v[0];
+endmodule

tests/simple/signed_full_slice.v

@@ -0,0 +1,29 @@
+module pass_through_a(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule
+
+module top_a(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_a pt(inp[31:0], out[31:0]);
+endmodule
+
+// tests both module declaration orderings
+
+module top_b(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_b pt(inp[31:0], out[31:0]);
+endmodule
+
+module pass_through_b(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule

tests/verilog/unbased_unsized_tern.sv

@@ -0,0 +1,31 @@
+module pass_through #(
+	parameter WIDTH = 1
+) (
+	input logic [WIDTH-1:0] inp,
+	output logic [WIDTH-1:0] out
+);
+	assign out = inp;
+endmodule
+
+module gate (
+	input logic inp,
+	output logic [63:0]
+		out1, out2, out3, out4
+);
+	pass_through #(40) pt1('1, out1);
+	pass_through #(40) pt2(inp ? '1 : '0, out2);
+	pass_through #(40) pt3(inp ? '1 : 2'b10, out3);
+	pass_through #(40) pt4(inp ? '1 : inp, out4);
+endmodule
+
+module gold (
+	input logic inp,
+	output logic [63:0]
+		out1, out2, out3, out4
+);
+	localparam ONES = 40'hFF_FFFF_FFFF;
+	pass_through #(40) pt1(ONES, out1);
+	pass_through #(40) pt2(inp ? ONES : 0, out2);
+	pass_through #(40) pt3(inp ? ONES : 2'sb10, out3);
+	pass_through #(40) pt4(inp ? ONES : inp, out4);
+endmodule

tests/verilog/unbased_unsized_tern.ys

@@ -0,0 +1,6 @@
+read_verilog -sv unbased_unsized_tern.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert