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verilog: use derived module info to elaborate cell connections

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- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
This commit is contained in:
Zachary Snow 2021-10-19 18:46:26 -06:00 • committed by Zachary Snow
parent bd16d01c0e
commit e833c6a418
15 changed files with 397 additions and 42 deletions
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1
kernel/constids.inc
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@ -163,6 +163,7 @@ X(RD_TRANSPARENCY_MASK)
X(RD_TRANSPARENT)
X(RD_WIDE_CONTINUATION)
X(reg)
X(reprocess_after)
X(S)
X(SET)
X(SET_POLARITY)