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https://github.com/YosysHQ/yosys
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verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
This commit is contained in:
Zachary Snow
Zachary Snow
parent
bd16d01c0e
commit
e833c6a418
15 changed files with 397 additions and 42 deletions
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@ -564,6 +564,115 @@ static std::string prefix_id(const std::string &prefix, const std::string &str)
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return prefix + str;
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}
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// direct access to this global should be limited to the following two functions
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static const RTLIL::Design *simplify_design_context = nullptr;
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void AST::set_simplify_design_context(const RTLIL::Design *design)
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{
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log_assert(!simplify_design_context || !design);
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simplify_design_context = design;
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}
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// lookup the module with the given name in the current design context
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static const RTLIL::Module* lookup_module(const std::string &name)
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{
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return simplify_design_context->module(name);
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}
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const RTLIL::Module* AstNode::lookup_cell_module()
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{
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log_assert(type == AST_CELL);
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auto reprocess_after = [this] (const std::string &modname) {
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if (!attributes.count(ID::reprocess_after))
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attributes[ID::reprocess_after] = AstNode::mkconst_str(modname);
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};
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const AstNode *celltype = nullptr;
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for (const AstNode *child : children)
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if (child->type == AST_CELLTYPE) {
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celltype = child;
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break;
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}
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log_assert(celltype != nullptr);
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const RTLIL::Module *module = lookup_module(celltype->str);
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if (!module)
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module = lookup_module("$abstract" + celltype->str);
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if (!module) {
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if (celltype->str.at(0) != '$')
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reprocess_after(celltype->str);
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return nullptr;
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}
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// build a mapping from true param name to param value
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size_t para_counter = 0;
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dict<RTLIL::IdString, RTLIL::Const> cell_params_map;
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for (AstNode *child : children) {
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if (child->type != AST_PARASET)
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continue;
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if (child->str.empty() && para_counter >= module->avail_parameters.size())
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return nullptr; // let hierarchy handle this error
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IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++] : child->str;
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const AstNode *value = child->children[0];
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if (value->type != AST_REALVALUE && value->type != AST_CONSTANT)
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return nullptr; // let genrtlil handle this error
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cell_params_map[paraname] = value->asParaConst();
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}
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// put the parameters in order and generate the derived module name
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std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
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for (RTLIL::IdString param : module->avail_parameters) {
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auto it = cell_params_map.find(param);
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if (it != cell_params_map.end())
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named_parameters.emplace_back(it->first, it->second);
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}
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std::string modname = celltype->str;
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if (cell_params_map.size()) // not named_parameters to cover hierarchical defparams
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modname = derived_module_name(celltype->str, named_parameters);
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// try to find the resolved module
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module = lookup_module(modname);
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if (!module) {
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reprocess_after(modname);
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return nullptr;
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}
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return module;
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}
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// returns whether an expression contains an unbased unsized literal; does not
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// check the literal exists in a self-determined context
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static bool contains_unbased_unsized(const AstNode *node)
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{
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if (node->type == AST_CONSTANT)
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return node->is_unsized;
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for (const AstNode *child : node->children)
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if (contains_unbased_unsized(child))
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return true;
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return false;
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}
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// adds a wire to the current module with the given name that matches the
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// dimensions of the given wire reference
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void add_wire_for_ref(const RTLIL::Wire *ref, const std::string &str)
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{
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AstNode *left = AstNode::mkconst_int(ref->width - 1 + ref->start_offset, true);
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AstNode *right = AstNode::mkconst_int(ref->start_offset, true);
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if (ref->upto)
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std::swap(left, right);
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AstNode *range = new AstNode(AST_RANGE, left, right);
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AstNode *wire = new AstNode(AST_WIRE, range);
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wire->is_signed = ref->is_signed;
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wire->is_logic = true;
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wire->str = str;
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current_ast_mod->children.push_back(wire);
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current_scope[str] = wire;
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}
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// convert the AST into a simpler AST that has all parameters substituted by their
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// values, unrolled for-loops, expanded generate blocks, etc. when this function
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// is done with an AST it can be converted into RTLIL using genRTLIL().
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@ -920,19 +1029,110 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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}
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if (type == AST_ARGUMENT)
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{
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if (children.size() == 1 && children[0]->type == AST_CONSTANT)
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{
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// HACK: For port bindings using unbased unsized literals, mark them
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// signed so they sign-extend. The hierarchy will still incorrectly
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// generate a warning complaining about resizing the expression.
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// This also doesn't handle the complex of something like a ternary
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// expression bound to a port, where the actual size of the port is
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// needed to resolve the expression correctly.
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AstNode *arg = children[0];
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if (arg->is_unsized)
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arg->is_signed = true;
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if (type == AST_CELL) {
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bool lookup_suggested = false;
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for (AstNode *child : children) {
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// simplify any parameters to constants
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if (child->type == AST_PARASET)
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while (child->simplify(true, false, false, 1, -1, false, true)) { }
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// look for patterns which _may_ indicate ambiguity requiring
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// resolution of the underlying module
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if (child->type == AST_ARGUMENT) {
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if (child->children.size() != 1)
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continue;
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const AstNode *value = child->children[0];
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if (value->type == AST_IDENTIFIER) {
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const AstNode *elem = value->id2ast;
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if (elem == nullptr) {
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if (current_scope.count(value->str))
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elem = current_scope.at(value->str);
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else
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continue;
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}
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if (elem->type == AST_MEMORY)
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// need to determine is the is a read or wire
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lookup_suggested = true;
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else if (elem->type == AST_WIRE && elem->is_signed && !value->children.empty())
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// this may be a fully sliced signed wire which needs
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// to be indirected to produce an unsigned connection
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lookup_suggested = true;
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}
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else if (contains_unbased_unsized(value))
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// unbased unsized literals extend to width of the context
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lookup_suggested = true;
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}
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}
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const RTLIL::Module *module = nullptr;
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if (lookup_suggested)
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module = lookup_cell_module();
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if (module) {
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size_t port_counter = 0;
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for (AstNode *child : children) {
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if (child->type != AST_ARGUMENT)
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continue;
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// determine the full name of port this argument is connected to
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RTLIL::IdString port_name;
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if (child->str.size())
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port_name = child->str;
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else {
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if (port_counter >= module->ports.size())
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log_file_error(filename, location.first_line,
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"Cell instance has more ports than the module!\n");
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port_name = module->ports[port_counter++];
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}
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// find the port's wire in the underlying module
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const RTLIL::Wire *ref = module->wire(port_name);
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if (ref == nullptr)
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log_file_error(filename, location.first_line,
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"Cell instance refers to port %s which does not exist in module %s!.\n",
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log_id(port_name), log_id(module->name));
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// select the argument, if present
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log_assert(child->children.size() <= 1);
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if (child->children.empty())
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continue;
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AstNode *arg = child->children[0];
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// plain identifiers never need indirection; this also prevents
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// adding infinite levels of indirection
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if (arg->type == AST_IDENTIFIER && arg->children.empty())
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continue;
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// only add indirection for standard inputs or outputs
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if (ref->port_input == ref->port_output)
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continue;
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did_something = true;
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// create the indirection wire
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std::stringstream sstr;
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sstr << "$indirect$" << ref->name.c_str() << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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std::string tmp_str = sstr.str();
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add_wire_for_ref(ref, tmp_str);
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AstNode *asgn = new AstNode(AST_ASSIGN);
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current_ast_mod->children.push_back(asgn);
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AstNode *ident = new AstNode(AST_IDENTIFIER);
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ident->str = tmp_str;
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child->children[0] = ident->clone();
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if (ref->port_input && !ref->port_output) {
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asgn->children.push_back(ident);
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asgn->children.push_back(arg);
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} else {
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log_assert(!ref->port_input && ref->port_output);
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asgn->children.push_back(arg);
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asgn->children.push_back(ident);
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}
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}
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}
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}
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