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https://github.com/YosysHQ/yosys
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Remove .c_str() from stringf parameters
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parent
acac60302d
commit
e7f210b817
90 changed files with 773 additions and 773 deletions
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@ -129,7 +129,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
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message += vstringf(msg, args);
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if (log_verific_callback) {
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string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str());
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string full_message = stringf("%s%s\n", message_prefix, message);
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#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
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log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile),
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linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0,
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@ -232,7 +232,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
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{
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std::string s = stringf("$verific$%s", obj->Name());
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if (obj->Linefile())
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s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())).c_str(), Verific::LineFile::GetLineNo(obj->Linefile()));
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s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())), Verific::LineFile::GetLineNo(obj->Linefile()));
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s += stringf("$%d", autoidx++);
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return s;
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}
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@ -472,7 +472,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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if (nl->IsFromVerilog()) {
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auto const value = verific_const(type_name, v, nl, false);
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attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
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attributes.emplace(stringf("\\enum_value_%s", value.as_string()), RTLIL::escape_id(k));
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}
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#ifdef VERIFIC_VHDL_SUPPORT
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else if (nl->IsFromVhdl()) {
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@ -1926,7 +1926,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
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RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
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RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
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RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memrd));
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cell->parameters[ID::MEMID] = memory->name.str();
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cell->parameters[ID::CLK_ENABLE] = false;
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cell->parameters[ID::CLK_POLARITY] = true;
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@ -1956,7 +1956,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
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RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
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RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
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RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memwr));
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cell->parameters[ID::MEMID] = memory->name.str();
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cell->parameters[ID::CLK_ENABLE] = false;
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cell->parameters[ID::CLK_POLARITY] = true;
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@ -1031,12 +1031,12 @@ struct VerificSvaImporter
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[[noreturn]] void parser_error(std::string errmsg, linefile_type loc)
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{
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parser_error(stringf("%s at %s:%d.\n", errmsg.c_str(), LineFile::GetFileName(loc), LineFile::GetLineNo(loc)));
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parser_error(stringf("%s at %s:%d.\n", errmsg, LineFile::GetFileName(loc), LineFile::GetLineNo(loc)));
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}
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[[noreturn]] void parser_error(std::string errmsg, Instance *inst)
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{
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parser_error(stringf("%s at %s (%s)", errmsg.c_str(), inst->View()->Owner()->Name(), inst->Name()), inst->Linefile());
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parser_error(stringf("%s at %s (%s)", errmsg, inst->View()->Owner()->Name(), inst->Name()), inst->Linefile());
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}
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[[noreturn]] void parser_error(Instance *inst)
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