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DSP48E1 sim model: seq test working

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-08-08 10:52:04 +01:00
parent f6605c7dc0
commit e7dbe7bb3d
3 changed files with 60 additions and 16 deletions
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2
techlibs/xilinx/tests/test_dsp_model.sh
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@ -4,7 +4,7 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v >
if [ ! -f "test_dsp_model_ref.v" ]; then
cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
fi
for tb in mult_noreg_nopreadd_nocasc
for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc
do
iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
vvp -N ./test_dsp_model