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https://github.com/YosysHQ/yosys
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Hook up $aldff support in various passes.
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parent
ba0723cad7
commit
e7d89e653c
9 changed files with 77 additions and 11 deletions
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@ -865,7 +865,7 @@ struct BtorWorker
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log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
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if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
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log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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@ -206,6 +206,7 @@ bool is_ff_cell(RTLIL::IdString type)
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return type.in(
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ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
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ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
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ID($aldff), ID($aldffe),
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ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
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}
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@ -1267,6 +1268,20 @@ struct CxxrtlWorker {
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dec_indent();
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f << indent << "}\n";
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}
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if (cell->hasPort(ID::ALOAD)) {
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// Asynchronous load
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID::ALOAD));
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f << " == value<1> {" << cell->getParam(ID::ALOAD_POLARITY).as_bool() << "u}) {\n";
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inc_indent();
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID::Q));
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f << " = ";
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dump_sigspec_rhs(cell->getPort(ID::AD));
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f << ";\n";
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dec_indent();
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f << indent << "}\n";
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}
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if (cell->hasPort(ID::SET)) {
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// Asynchronous set (for individual bits)
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f << indent;
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@ -2573,7 +2588,7 @@ struct CxxrtlWorker {
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flow.add_node(cell);
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// Various DFF cells are treated like posedge/negedge processes, see above for details.
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if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
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if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
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if (is_valid_clock(cell->getPort(ID::CLK)))
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register_edge_signal(sigmap, cell->getPort(ID::CLK),
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cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
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@ -860,7 +860,7 @@ struct Smt2Worker
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log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smt2`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
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if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
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log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smt2`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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@ -578,7 +578,7 @@ struct SmvWorker
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log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
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if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
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log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smv`.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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