mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-19 20:33:39 +00:00
Code Activity

added destructors for wires and cells

Browse source
This commit is contained in:
Benedikt Tutzer 2018-07-10 08:52:36 +02:00
parent 55df7fff19
commit e7d3f3cd46
2 changed files with 16 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

14
kernel/rtlil.cc
View file

@ -2223,6 +2223,13 @@ RTLIL::Wire::Wire()
#endif
}
RTLIL::Wire::~Wire()
{
#ifdef WITH_PYTHON
RTLIL::Wire::get_all_wires()->erase(hashidx_);
#endif
}
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>();
std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
@ -2256,6 +2263,13 @@ RTLIL::Cell::Cell() : module(nullptr)
#endif
}
RTLIL::Cell::~Cell()
{
#ifdef WITH_PYTHON
RTLIL::Cell::get_all_cells()->erase(hashidx_);
#endif
}
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>();
std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)