diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt
index 209f232c7..9a5111490 100644
--- a/techlibs/analogdevices/brams.txt
+++ b/techlibs/analogdevices/brams.txt
@@ -1,20 +1,38 @@
+# family:        T16FFC            T40LP
+# BRAM:          RBRAM2            RBRAM
+# Supported:     SDP_8192x05       SDP_4096x05
+#                SDP_4096x10       SDP_2048x10
+#                SDP_2048x40       SDP_1024x40
+# Ignored:       SDP_4096x09       SDP_2048x09
+# Unimplemented: SP_2048x20        SP_1024x20
+#                TDP_4096x09
+#                TDP_8192x05
+#                TDP_2048x40
+#                SP2_2048x09       SP2_1024x09
+#                SP2_4096x05       SP2_2048x05
+
+
 # Simple Dual Port
-# Supported:
-# SDP_4096x05
-# SDP_2048x10
-# SDP_1024x40
-# Ignored:
-# SDP_2048x09
 
 ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
 	option "ENABLE_WIDTH" "BIT" {
-		abits 12;
+		ifdef IS_T40LP {
+			abits 12;
+		}
+		ifdef IS_T16FFC {
+			abits 13;
+		}
 		widths 5 10 global;
 		byte 1;
 		cost 1;
 	}
 	option "ENABLE_WIDTH" "BYTE" {
-		abits 10;
+		ifdef IS_T40LP {
+			abits 10;
+		}
+		ifdef IS_T16FFC {
+			abits 11;
+		}
 		width 40;
 		byte 8;
 		cost 4;
@@ -32,8 +50,7 @@ ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
 }
 
 # Single Port
-# SP_1024x20
+
+# True Dual Port
 
 # Dual Single Port
-# SP2_1024x09
-# SP2_2048x05
diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v
index 6d590501e..b2ba6b77d 100644
--- a/techlibs/analogdevices/brams_map.v
+++ b/techlibs/analogdevices/brams_map.v
@@ -4,6 +4,18 @@ parameter INIT = 0;
 parameter OPTION_ENABLE_WIDTH = "BIT";
 parameter WIDTH = 40;
 
+`ifdef IS_T40LP
+parameter ABITS = 12;
+localparam NODE = "T40LP_Gen2.4";
+localparam BRAM_MODE = WIDTH ==  5 ? "SDP_4096x05" :
+	WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40";
+`elsif IS_T16FFC
+parameter ABITS = 13;
+localparam NODE = "T16FFC_Gen2.4";
+localparam BRAM_MODE = WIDTH ==  5 ? "SDP_8192x05" :
+	WIDTH == 10 ? "SDP_4096x10" : "SDP_2048x40";
+`endif
+
 parameter PORT_W_WR_EN_WIDTH = 5;
 parameter PORT_W_CLK_POL = 1;
 
@@ -11,30 +23,32 @@ parameter PORT_R_CLK_POL = 1;
 
 input PORT_W_CLK;
 input PORT_W_CLK_EN;
-input [11:0] PORT_W_ADDR;
+input [ABITS-1:0] PORT_W_ADDR;
 input [WIDTH-1:0] PORT_W_WR_DATA;
 input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
 
 input PORT_R_CLK;
 input PORT_R_CLK_EN;
-input [11:0] PORT_R_ADDR;
+input [ABITS-1:0] PORT_R_ADDR;
 output [WIDTH-1:0] PORT_R_RD_DATA;
 
+`ifdef IS_T40LP
 RBRAM
+`endif
+`ifdef IS_T16FFC
+RBRAM2
+`endif
 #(
-	.TARGET_NODE("T40LP_Gen2.4"),
-	.BRAM_MODE(
-		WIDTH ==  5 ? "SDP_4096x05" :
-		WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40"
-	),
+	.TARGET_NODE(NODE),
+	.BRAM_MODE(BRAM_MODE),
 	.QA_REG(0),
 	.QB_REG(0),
 	.CLKA_INV(!PORT_W_CLK_POL),
 	.CLKB_INV(!PORT_R_CLK_POL),
 	.DATA_WIDTH(WIDTH),
 	.ADDR_WIDTH(
-		WIDTH ==  5 ? 12 :
-		WIDTH == 10 ? 11 : 10
+		WIDTH ==  5 ? ABITS :
+		WIDTH == 10 ? ABITS-1 : ABITS-2
 	),
 	.WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH),
 	.PERR_WIDTH(1),
@@ -47,7 +61,7 @@ _TECHMAP_REPLACE_
 	.WEA(PORT_W_WR_EN),
 	.AA(
 		WIDTH ==  5 ? PORT_W_ADDR :
-		WIDTH == 10 ? PORT_W_ADDR[11:1] : PORT_W_ADDR[11:2]
+		WIDTH == 10 ? PORT_W_ADDR[ABITS-1:1] : PORT_W_ADDR[ABITS-1:2]
 	),
 	.CLKA(PORT_W_CLK),
 	.QB(PORT_R_RD_DATA),
@@ -56,7 +70,7 @@ _TECHMAP_REPLACE_
 	// .WEB(0),
 	.AB(
 		WIDTH ==  5 ? PORT_R_ADDR :
-		WIDTH == 10 ? PORT_R_ADDR[11:1] : PORT_R_ADDR[11:2]
+		WIDTH == 10 ? PORT_R_ADDR[ABITS-1:1] : PORT_R_ADDR[ABITS-1:2]
 	),
 	.CLKB(PORT_R_CLK),
 );
diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v
index 69791cf03..0a2fadc7d 100644
--- a/techlibs/analogdevices/cells_sim.v
+++ b/techlibs/analogdevices/cells_sim.v
@@ -1497,7 +1497,47 @@ module RBRAM #(
     parameter CLKB_INV = 0,
     parameter DATA_WIDTH = 40,
     parameter ADDR_WIDTH = 12,
-    parameter WE_WIDTH = 10,
+    parameter WE_WIDTH = 20,
+    parameter PERR_WIDTH = 4,
+) (
+    output [DATA_WIDTH-1:0] QA,
+    input [DATA_WIDTH-1:0] DA,
+    input CEA,
+    input [WE_WIDTH-1:0] WEA,
+    input [ADDR_WIDTH-1:0] AA,
+    (* clkbuf_sink *)
+    (* invertible_pin = "CLKA_INV" *)
+    input CLKA,
+    output [DATA_WIDTH-1:0] QB,
+    input [DATA_WIDTH-1:0] DB,
+    input CEB,
+    input [WE_WIDTH-1:0] WEB,
+    input [ADDR_WIDTH-1:0] AB,
+    (* clkbuf_sink *)
+    (* invertible_pin = "CLKB_INV" *)
+    input CLKB,
+    output reg [PERR_WIDTH-1:0] PERRA,
+    output reg [PERR_WIDTH-1:0] PERRB,
+    output SBEA,
+    output SBEB,
+    output MBEA,
+    output MBEB,
+    input SLP,
+    input PD,
+);
+
+endmodule
+
+module RBRAM2 #(
+    parameter TARGET_NODE = "T16FFC_Gen2.4",
+    parameter BRAM_MODE = "SDP_2048x40",
+    parameter QA_REG = 0,
+    parameter QB_REG = 0,
+    parameter CLKA_INV = 0,
+    parameter CLKB_INV = 0,
+    parameter DATA_WIDTH = 40,
+    parameter ADDR_WIDTH = 13,
+    parameter WE_WIDTH = 20,
     parameter PERR_WIDTH = 4,
 ) (
     output [DATA_WIDTH-1:0] QA,
diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc
index 09406fbf1..6a1d471b6 100644
--- a/techlibs/analogdevices/synth_analogdevices.cc
+++ b/techlibs/analogdevices/synth_analogdevices.cc
@@ -48,6 +48,13 @@ struct SynthAnalogDevicesPass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
+		log("    -tech <tech>\n");
+		log("        run synthesis for the specified ADI technology process\n");
+		log("        currently only affects the type of BRAM used.\n");
+		log("        supported values:\n");
+		log("        - t40lp (RBRAM)\n");
+		log("        - t16ffc (RBRAM2, default)\n");
+		log("\n");
 		log("    -edif <file>\n");
 		log("        write the design to the specified edif file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -107,7 +114,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
 		log("\n");
 	}
 
-	std::string top_opt, edif_file, json_file;
+	std::string top_opt, edif_file, json_file, tech;
 	bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp;
 	bool abc9, dff;
 	bool flatten_before_abc;
@@ -118,6 +125,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
 	{
 		top_opt = "-auto-top";
 		edif_file.clear();
+		tech = "t16ffc";
 		flatten = true;
 		retime = false;
 		noiopad = false;
@@ -147,6 +155,10 @@ struct SynthAnalogDevicesPass : public ScriptPass
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-tech" && argidx+1 < args.size()) {
+				tech = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
@@ -231,6 +243,9 @@ struct SynthAnalogDevicesPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
+		if (!(tech == "t16ffc" || tech == "t40lp"))
+			log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech);
+
 		if (widemux != 0 && widemux < 2)
 			log_cmd_error("-widemux value must be 0 or >= 2.\n");
 
@@ -334,8 +349,8 @@ struct SynthAnalogDevicesPass : public ScriptPass
 
 		if (check_label("map_memory")) {
 			std::string params = "";
-			std::string lutrams_map = "+/analogdevices/lutrams_<family>_map.v";
-			std::string brams_map = "+/analogdevices/brams_<family>_map.v";
+			std::string lutrams_map = "+/analogdevices/lutrams_map.v";
+			std::string brams_map = "+/analogdevices/brams_map.v";
 			if (help_mode) {
 				params = " [...]";
 			} else {
@@ -344,6 +359,13 @@ struct SynthAnalogDevicesPass : public ScriptPass
 				lutrams_map = "+/analogdevices/lutrams_map.v";
 				params += " -lib +/analogdevices/brams.txt";
 				brams_map = "+/analogdevices/brams_map.v";
+				if (tech == "t16ffc") {
+					params += " -D IS_T16FFC";
+					brams_map += " -D IS_T16FFC";
+				} else if (tech == "t40lp") {
+					params += " -D IS_T40LP";
+					brams_map += " -D IS_T40LP";
+				}
 				if (nolutram)
 					params += " -no-auto-distributed";
 				if (nobram)