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write_verilog: Use assign for $buf

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Martin Povišer 2024-12-05 16:27:44 +01:00
parent 66734f522d
commit e7b21d2706
1 changed files with 1 additions and 1 deletions
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2
backends/verilog/verilog_backend.cc
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@ -1071,7 +1071,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == ID($_BUF_)) { if (cell->type.in(ID($_BUF_), ID($buf))) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");