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	Add "verific -vlog-incdir" and "verific -vlog-define"
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					 1 changed files with 35 additions and 0 deletions
				
			
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			@ -1851,6 +1851,16 @@ struct VerificPass : public Pass {
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		log("Load the specified VHDL files into Verific.\n");
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		log("\n");
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		log("\n");
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		log("    verific -vlog-incdir <directory>..\n");
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		log("\n");
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		log("Add Verilog include directories.\n");
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		log("\n");
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		log("\n");
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		log("    verific -vlog-define <macro>[=<value>]..\n");
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		log("\n");
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		log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
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		log("\n");
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		log("\n");
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		log("    verific -import [options] <top-module>..\n");
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		log("\n");
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		log("Elaborate the design for the specified top modules, import to Yosys and\n");
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			@ -1909,6 +1919,8 @@ struct VerificPass : public Pass {
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		Message::RegisterCallBackMsg(msg_func);
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		RuntimeFlags::SetVar("db_allow_external_nets", 1);
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		RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
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		veri_file::DefineCmdLineMacro("VERIFIC");
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		veri_file::DefineCmdLineMacro("SYNTHESIS");
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		const char *release_str = Message::ReleaseString();
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		time_t release_time = Message::ReleaseDate();
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			@ -1924,6 +1936,27 @@ struct VerificPass : public Pass {
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		int argidx = 1;
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		if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
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			for (argidx++; argidx < GetSize(args); argidx++)
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				veri_file::AddIncludeDir(args[argidx].c_str());
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			goto check_error;
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		}
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		if (GetSize(args) > argidx && args[argidx] == "-vlog-define") {
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			for (argidx++; argidx < GetSize(args); argidx++) {
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				string name = args[argidx];
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				size_t equal = name.find('=');
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				if (equal != std::string::npos) {
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					string value = name.substr(equal+1);
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					name = name.substr(0, equal);
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					veri_file::DefineCmdLineMacro(name.c_str(), value.c_str());
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				} else {
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					veri_file::DefineCmdLineMacro(name.c_str());
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				}
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			}
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			goto check_error;
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		}
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		if (GetSize(args) > argidx && args[argidx] == "-vlog95") {
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			for (argidx++; argidx < GetSize(args); argidx++)
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				if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_95))
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			@ -2139,6 +2172,8 @@ struct VerificPass : public Pass {
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				nl_done.insert(nl);
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			}
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			veri_file::Reset();
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			vhdl_file::Reset();
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			Libset::Reset();
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			goto check_error;
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		}
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