From e78e19acfe39c3f7cd188df1d8a9728d1dad21e5 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 19 May 2026 16:21:00 +0200
Subject: [PATCH] patch: fix patch mixins

---
 kernel/rtlil.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 134082585..aa8852586 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -22,6 +22,7 @@
 #include "kernel/newcelltypes.h"
 #include "kernel/binding.h"
 #include "kernel/sigtools.h"
+#include "kernel/unstable/patch.h"
 #include "kernel/threading.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "frontends/verilog/preproc.h"
@@ -5945,5 +5946,6 @@ std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
 #endif
 
 template class CellAdderMixin<RTLIL::Module>;
+template class CellAdderMixin<RTLIL::Patch>;
 
 YOSYS_NAMESPACE_END