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Merge pull request #6006 from YosysHQ/slang-promote

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Add slang information in README
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Miodrag Milanović 2026-07-07 13:39:48 +00:00 • committed by GitHub
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2 changed files with 14 additions and 5 deletions
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9
README.md
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@ -5,6 +5,9 @@ This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.
Yosys is using [sv-elab](https://github.com/povik/sv-elab) and [slang](https://github.com/MikePopoloski/slang) libraries to provide comprehensive SystemVerilog support.
It supports an (informally defined) synthesizable subset of SystemVerilog in version IEEE 1800-2017 or IEEE 1800-2023.
Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
@ -67,13 +70,9 @@ on Read the Docs.
When cloning Yosys, some required libraries are included as git submodules. Make
sure to call e.g.
$ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git
or
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys
$ git submodule update --init --recursive
$ git submodule update --init
A C++ compiler with C++20 support is required as well as some standard tools
such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake

10
libs/CMakeLists.txt
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@ -43,5 +43,15 @@ block()
if(NOT Boost_FOUND)
target_compile_definitions(slang_slang PRIVATE BOOST_REGEX_STANDALONE)
endif()
if (SLANG_INCLUDE_TOOLS)
# Temporary to prevent build issues
set_target_properties(slang_tidy_obj_lib PROPERTIES YOSYS_IS_ABC ON)
install(TARGETS slang_driver RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})
install(TARGETS slang_hier RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})
install(TARGETS slang_reflect RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})
install(TARGETS rewriter RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})
install(TARGETS slang_tidy RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})
endif()
endif()
endblock()