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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/master' into xc7dsp
This commit is contained in:
Eddie Hung
commit
e742478e1d
28 changed files with 717 additions and 213 deletions
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@ -184,14 +184,6 @@ module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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`ifdef _ABC
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(* abc_box_id = 3, lib_whitebox *)
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module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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assign O = S1 ? (S0 ? I3 : I2)
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: (S0 ? I1 : I0);
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endmodule
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`endif
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module XORCY(output O, input CI, LI);
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assign O = CI ^ LI;
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endmodule
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@ -236,7 +228,15 @@ endmodule
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`endif
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module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
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module FDRE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -248,7 +248,13 @@ module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
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endcase endgenerate
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endmodule
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module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
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module FDSE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -260,7 +266,13 @@ module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
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endcase endgenerate
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endmodule
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module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
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module FDCE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -274,7 +286,13 @@ module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
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endcase endgenerate
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endmodule
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module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
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module FDPE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -288,38 +306,61 @@ module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
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endcase endgenerate
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endmodule
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module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
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module FDRE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
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endmodule
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module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
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module FDSE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
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endmodule
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module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
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module FDCE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
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module FDPE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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endmodule
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(* abc_box_id = 5 *)
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module RAM32X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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(* abc_scc_break *)
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *)
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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@ -335,14 +376,13 @@ module RAM32X1D (
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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(* abc_box_id = 6 *)
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module RAM64X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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(* abc_scc_break *)
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *)
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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@ -358,14 +398,13 @@ module RAM64X1D (
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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(* abc_box_id = 7 *)
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module RAM128X1D (
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output DPO, SPO,
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(* abc_scc_break *)
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *)
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input WE,
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input [6:0] A, DPRA
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);
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@ -379,6 +418,8 @@ module RAM128X1D (
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc_arrival=1472 *)
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output Q,
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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@ -423,7 +464,10 @@ module SRLC16E (
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endmodule
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module SRLC32E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc_arrival=1472 *)
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output Q,
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(* abc_arrival=1114 *)
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output Q31,
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input [4:0] A,
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input CE,
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