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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-19 11:37:12 +02:00
parent 54a3baa2de
commit e71ed3007d
8 changed files with 49 additions and 55 deletions
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6
passes/cmds/dump_twines.cc
View file

@ -41,9 +41,9 @@ struct DumpTwinesPass : public Pass {
const TwinePool &pool = design->twines;
log("twine pool: %zu local nodes\n", pool.size());
for (auto it = pool.backing.begin(); it != pool.backing.end(); ++it) {
TwineRef id = STATIC_TWINE_END + pool.backing.get_index(it);
const Twine &n = *it;
for (size_t idx = 0; idx < pool.backing.size(); ++idx) {
TwineRef id = STATIC_TWINE_END + idx;
const Twine &n = pool.backing[idx];
if (n.is_leaf()) {
log(" @%zu leaf \"%s\"", (size_t)id, n.leaf().c_str());
} else if (n.is_suffix()) {

16
passes/cmds/select.cc
View file

@ -685,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
{
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
return;
if (sel.full_selection) {
@ -848,7 +848,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
select_blackboxes = true;
}
if (design->selected_active_module) {
if (design->selected_active_module != Twine::Null) {
arg_mod = design->twines.str(design->selected_active_module);
arg_memb = arg;
if (!isprefixed(arg_memb))
@ -1524,7 +1524,7 @@ struct SelectPass : public Pass {
if (clear_mode) {
design->selection() = RTLIL::Selection::FullSelection(design);
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1733,7 +1733,7 @@ struct CdPass : public Pass {
if (args.size() == 1 || args[1] == "/") {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1743,7 +1743,7 @@ struct CdPass : public Pass {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
TwineSearch search(&design->twines);
while (1)
@ -1774,10 +1774,10 @@ struct CdPass : public Pass {
TwineSearch search(&design->twines);
TwineRef modname = search.find(RTLIL::escape_id(args[1]));
if (design->module(modname) == nullptr && design->selected_active_module) {
if (design->module(modname) == nullptr && design->selected_active_module != Twine::Null) {
RTLIL::Module *module = design->module(design->selected_active_module);
TwineRef cell_ref = modname;
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
if (module != nullptr && cell_ref != Twine::Null && module->cell(cell_ref) != nullptr)
modname = module->cell(cell_ref)->type_impl;
}
@ -1837,7 +1837,7 @@ struct LsPass : public Pass {
size_t argidx = 1;
extra_args(args, argidx, design);
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
{
std::vector<IdString> matches;