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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-19 11:37:12 +02:00
parent 54a3baa2de
commit e71ed3007d
8 changed files with 49 additions and 55 deletions
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6
passes/cmds/dump_twines.cc
View file

@ -41,9 +41,9 @@ struct DumpTwinesPass : public Pass {
const TwinePool &pool = design->twines;
log("twine pool: %zu local nodes\n", pool.size());
for (auto it = pool.backing.begin(); it != pool.backing.end(); ++it) {
TwineRef id = STATIC_TWINE_END + pool.backing.get_index(it);
const Twine &n = *it;
for (size_t idx = 0; idx < pool.backing.size(); ++idx) {
TwineRef id = STATIC_TWINE_END + idx;
const Twine &n = pool.backing[idx];
if (n.is_leaf()) {
log(" @%zu leaf \"%s\"", (size_t)id, n.leaf().c_str());
} else if (n.is_suffix()) {

16
passes/cmds/select.cc
View file

@ -685,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
{
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
return;
if (sel.full_selection) {
@ -848,7 +848,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
select_blackboxes = true;
}
if (design->selected_active_module) {
if (design->selected_active_module != Twine::Null) {
arg_mod = design->twines.str(design->selected_active_module);
arg_memb = arg;
if (!isprefixed(arg_memb))
@ -1524,7 +1524,7 @@ struct SelectPass : public Pass {
if (clear_mode) {
design->selection() = RTLIL::Selection::FullSelection(design);
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1733,7 +1733,7 @@ struct CdPass : public Pass {
if (args.size() == 1 || args[1] == "/") {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1743,7 +1743,7 @@ struct CdPass : public Pass {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
TwineSearch search(&design->twines);
while (1)
@ -1774,10 +1774,10 @@ struct CdPass : public Pass {
TwineSearch search(&design->twines);
TwineRef modname = search.find(RTLIL::escape_id(args[1]));
if (design->module(modname) == nullptr && design->selected_active_module) {
if (design->module(modname) == nullptr && design->selected_active_module != Twine::Null) {
RTLIL::Module *module = design->module(design->selected_active_module);
TwineRef cell_ref = modname;
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
if (module != nullptr && cell_ref != Twine::Null && module->cell(cell_ref) != nullptr)
modname = module->cell(cell_ref)->type_impl;
}
@ -1837,7 +1837,7 @@ struct LsPass : public Pass {
size_t argidx = 1;
extra_args(args, argidx, design);
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
{
std::vector<IdString> matches;

11
passes/equiv/equiv_make.cc
View file

@ -108,13 +108,13 @@ struct EquivMakeWorker
for (auto it : gold_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
gold_clone->rename(it, gold_clone->design->twines.add(std::string{it->name.str() + "_gold"}));
}
for (auto it : gold_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
gold_clone->rename(it, gold_clone->design->twines.add(std::string{it->name.str() + "_gold"}));
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gold_clone->remove(it);
}
@ -122,13 +122,13 @@ struct EquivMakeWorker
for (auto it : gate_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
gate_clone->rename(it, gate_clone->design->twines.add(std::string{it->name.str() + "_gate"}));
}
for (auto it : gate_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
gate_clone->rename(it, gate_clone->design->twines.add(std::string{it->name.str() + "_gate"}));
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gate_clone->remove(it);
}
@ -516,9 +516,8 @@ struct EquivMakePass : public Pass {
log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
worker.equiv_mod = design->addModule(design->twines.add(Twine{RTLIL::escape_id(args[argidx+2])}));
worker.equiv_mod = design->addModule(design->twines.add(std::string{RTLIL::escape_id(args[argidx+2])}));
worker.run();
Pass::call(design, "dump");
}
} EquivMakePass;

2
passes/hierarchy/flatten.cc
View file

@ -350,7 +350,7 @@ struct FlattenWorker
RTLIL::Cell *cell = worklist.back();
worklist.pop_back();
TwineRef cell_type_ref = design->twines.add(Twine{cell->type.str()});
TwineRef cell_type_ref = cell->type.ref();
if (!design->has(cell_type_ref))
continue;

2
passes/memory/memory_map.cc
View file

@ -263,7 +263,7 @@ struct MemoryMapWorker
if (module->wire(TwineSearch(&design->twines).find(w_out_name)) != nullptr)
w_out_name = genid(mem.memid, "", addr, "$q");
RTLIL::Wire *w_out = module->addWire(design->twines.add(Twine{w_out_name}), mem.width);
RTLIL::Wire *w_out = module->addWire(design->twines.add(std::string{w_out_name}), mem.width);
if (formal && mem.packed && mem.cell->name.isPublic()) {
auto hdlname = mem.cell->get_hdlname_attribute();

12
passes/sat/miter.cc
View file

@ -146,7 +146,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
{
if (gold_cross_ports.count(gold_wire))
{
SigSpec w = miter_module->addWire(Twine{"\\cross_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
SigSpec w = miter_module->addWire(design->twines.add(std::string{"\\cross_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
gold_cell->setPort(gold_wire->meta_->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_TWINE, GetSize(w));
@ -162,7 +162,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_input)
{
RTLIL::Wire *w = miter_module->addWire(Twine{"\\in_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w = miter_module->addWire(design->twines.add(std::string{"\\in_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w->port_input = true;
gold_cell->setPort(gold_wire->meta_->name, w);
@ -171,10 +171,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_output)
{
RTLIL::Wire *w_gold = miter_module->addWire(Twine{"\\gold_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w_gold = miter_module->addWire(design->twines.add(std::string{"\\gold_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w_gold->port_output = flag_make_outputs;
RTLIL::Wire *w_gate = miter_module->addWire(Twine{"\\gate_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w_gate = miter_module->addWire(design->twines.add(std::string{"\\gate_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w_gate->port_output = flag_make_outputs;
gold_cell->setPort(gold_wire->meta_->name, w_gold);
@ -247,7 +247,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_outcmp)
{
RTLIL::Wire *w_cmp = miter_module->addWire(Twine{"\\cmp_" + design->twines.str(gold_wire->meta_->name)});
RTLIL::Wire *w_cmp = miter_module->addWire(design->twines.add(std::string{"\\cmp_" + design->twines.unescaped_str(gold_wire->meta_->name)}));
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@ -255,7 +255,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_cover)
{
auto cover_condition = miter_module->Not(NEW_TWINE, this_condition);
miter_module->addCover(Twine{"\\cover_" + design->twines.str(gold_wire->meta_->name)}, cover_condition, State::S1);
miter_module->addCover(Twine{"\\cover_" + design->twines.unescaped_str(gold_wire->meta_->name)}, cover_condition, State::S1);
}
all_conditions.append(this_condition);