mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Standard compliance for tests/verilog/block_labels.ys

Browse source 
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
This commit is contained in:
CORRADI Quentin 2023-05-18 14:46:25 +01:00 • committed by Zachary Snow
parent 147cceb516
commit e7156c644d
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/verilog/block_labels.ys
View file

@ -1,7 +1,7 @@
read_verilog <<EOT read_verilog <<EOT
module foo; module foo;
genvar a = 0; genvar a;
for (a = 0; a < 10; a++) begin : a for (a = 0; a < 10; a++) begin : a
end : a end : a
endmodule endmodule
@ -9,7 +9,7 @@ EOT
read_verilog <<EOT read_verilog <<EOT
module foo2; module foo2;
genvar a = 0; genvar a;
for (a = 0; a < 10; a++) begin : a for (a = 0; a < 10; a++) begin : a
end end
endmodule endmodule
@ -19,7 +19,7 @@ logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
read_verilog <<EOT read_verilog <<EOT
module foo3; module foo3;
genvar a = 0; genvar a;
for (a = 0; a < 10; a++) begin : a for (a = 0; a < 10; a++) begin : a
end : b end : b
endmodule endmodule