mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 23:52:32 +00:00
Code Activity

rtlil: add Module* back-pointer to RTLIL::Memory

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-05 13:49:50 +02:00
parent 9ed93e210b
commit e70eed3296
7 changed files with 17 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
kernel/rtlil.h
View file

@ -2286,6 +2286,13 @@ struct RTLIL::Memory : public RTLIL::NamedObject
Memory();
// Back-pointer to the owning module — same role as Cell::module /
// Wire::module. Set by Module::addMemory / the frontends that
// construct Memory free-standing before attaching to a module.
// Lets Memory's src access (and the upcoming per-Design meta vector
// lookup) resolve uniformly via module->design.
RTLIL::Module *module = nullptr;
int width, start_offset, size;
#ifdef YOSYS_ENABLE_PYTHON
~Memory();