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Update tests

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This commit is contained in:
Miodrag Milanovic 2023-06-09 14:41:45 +02:00
parent 0d4a670267
commit e6f7cf3b29
7 changed files with 19 additions and 17 deletions
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tests/arch/ice40/rom.ys
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@ -4,5 +4,5 @@ flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 5 t:SB_LUT4
select -assert-max 6 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D