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kernel/mem: Introduce transparency masks.
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parent
681a1c07e5
commit
e6f3d1c225
8 changed files with 407 additions and 117 deletions
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@ -22,6 +22,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/mem.h"
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#include "kernel/ffinit.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -32,6 +33,7 @@ struct MemoryShareWorker
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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FfInitVals initvals;
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bool flag_widen;
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@ -106,8 +108,6 @@ struct MemoryShareWorker
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continue;
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if (port1.ce_over_srst != port2.ce_over_srst)
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continue;
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if (port1.transparent != port2.transparent)
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continue;
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// If the width of the ports doesn't match, they can still be
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// merged by widening the narrow one. Check if the conditions
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// hold for that.
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@ -147,8 +147,10 @@ struct MemoryShareWorker
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continue;
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if (!merge_rst_value(mem, srst_value, wide_log2, port1.srst_value, sub1, port2.srst_value, sub2))
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continue;
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// At this point we are committed to the merge.
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{
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log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
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mem.prepare_rd_merge(i, j, &initvals);
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mem.widen_prep(wide_log2);
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SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
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module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
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@ -231,7 +233,7 @@ struct MemoryShareWorker
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continue;
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}
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log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
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mem.prepare_wr_merge(i, j);
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mem.prepare_wr_merge(i, j, &initvals);
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port1.addr = sigmap_xmux(port1.addr);
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port2.addr = sigmap_xmux(port2.addr);
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mem.widen_wr_port(i, wide_log2);
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@ -391,7 +393,7 @@ struct MemoryShareWorker
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}
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log(" Merging port %d into port %d.\n", idx2, idx1);
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mem.prepare_wr_merge(idx1, idx2);
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mem.prepare_wr_merge(idx1, idx2, &initvals);
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port_to_sat_variable.at(idx1) = qcsat.ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
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RTLIL::SigSpec last_addr = port1.addr;
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@ -453,6 +455,7 @@ struct MemoryShareWorker
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this->module = module;
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sigmap.set(module);
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initvals.set(&sigmap, module);
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sigmap_xmux = sigmap;
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for (auto cell : module->cells())
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