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Fixed more issues with GreenPAK counter sim models

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This commit is contained in:
Andrew Zonenberg 2017-08-15 00:50:31 -07:00
parent 3a404be62a
commit e6eaf487b6
1 changed files with 23 additions and 19 deletions
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28
techlibs/greenpak4/cells_sim_digital.v
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@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
"RISING": begin "RISING": begin
always @(posedge CLK, posedge RST) begin always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(RST)
count <= 0;
end end
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK, negedge RST) begin always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(!RST)
count <= 0;
end end
end end
@ -422,23 +424,25 @@ module GP_COUNT8(
"RISING": begin "RISING": begin
always @(posedge CLK, posedge RST) begin always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(RST)
count <= 0;
end end
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK, negedge RST) begin always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(!RST)
count <= 0;
end end
end end