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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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2
passes/techmap/extract.cc
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@ -724,7 +724,7 @@ struct ExtractPass : public Pass {
RTLIL::Module *newMod = new RTLIL::Module;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
map->modules_[newMod->name] = newMod;
map->add(newMod);
int portCounter = 1;
for (auto wire : wires) {