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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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2
passes/sat/miter.cc
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@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name;
design->modules_[miter_name] = miter_module;
design->add(miter_module);
RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);