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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
mod->attributes["\\blackbox"] = RTLIL::Const(1);
design->modules_[mod->name] = mod;
design->add(mod);
for (auto &decl : ports) {
RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));

2
passes/hierarchy/submod.cc
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@ -105,7 +105,7 @@ struct SubmodWorker
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->name = submod.full_name;
design->modules_[new_mod->name] = new_mod;
design->add(new_mod);
int port_counter = 1, auto_name_counter = 1;
std::set<std::string> all_wire_names;