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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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5
passes/cmds/design.cc
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@ -198,6 +198,7 @@ struct DesignPass : public Pass {
delete copy_to_design->modules_.at(trg_name);
copy_to_design->modules_[trg_name] = mod->clone();
copy_to_design->modules_[trg_name]->name = trg_name;
copy_to_design->modules_[trg_name]->design = copy_to_design;
}
}
@ -206,7 +207,7 @@ struct DesignPass : public Pass {
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto &it : design->modules_)
design_copy->modules_[it.first] = it.second->clone();
design_copy->add(it.second->clone());
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
@ -242,7 +243,7 @@ struct DesignPass : public Pass {
pushed_designs.pop_back();
for (auto &it : saved_design->modules_)
design->modules_[it.first] = it.second->clone();
design->add(it.second->clone());
design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars;