mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Added module->design and cell->module, wire->module pointers

Browse source
This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/cmds/copy.cc
View file

@ -47,8 +47,9 @@ struct CopyPass : public Pass {
if (design->modules_.count(trg_name) != 0)
log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
design->modules_[trg_name] = design->modules_.at(src_name)->clone();
design->modules_[trg_name]->name = trg_name;
RTLIL::Module *new_mod = design->module(src_name)->clone();
new_mod->name = trg_name;
design->add(new_mod);
}
} CopyPass;