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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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2
passes/abc/blifparse.cc
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@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
int port_count = 0;
module->name = "\\netlist";
design->modules_[module->name] = module;
design->add(module);
size_t buffer_size = 4096;
char *buffer = (char*)malloc(buffer_size);