Added module->design and cell->module, wire->module pointers

passes/abc/blifparse.cc

@@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 
 	int port_count = 0;
 	module->name = "\\netlist";
-	design->modules_[module->name] = module;
+	design->add(module);
 
 	size_t buffer_size = 4096;
 	char *buffer = (char*)malloc(buffer_size);

passes/cmds/copy.cc

@@ -47,8 +47,9 @@ struct CopyPass : public Pass {
 		if (design->modules_.count(trg_name) != 0)
 			log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
 
-		design->modules_[trg_name] = design->modules_.at(src_name)->clone();
-		design->modules_[trg_name]->name = trg_name;
+		RTLIL::Module *new_mod = design->module(src_name)->clone();
+		new_mod->name = trg_name;
+		design->add(new_mod);
 	}
 } CopyPass;
  

passes/cmds/design.cc

@@ -198,6 +198,7 @@ struct DesignPass : public Pass {
 					delete copy_to_design->modules_.at(trg_name);
 				copy_to_design->modules_[trg_name] = mod->clone();
 				copy_to_design->modules_[trg_name]->name = trg_name;
+				copy_to_design->modules_[trg_name]->design = copy_to_design;
 			}
 		}
 
@@ -206,7 +207,7 @@ struct DesignPass : public Pass {
 			RTLIL::Design *design_copy = new RTLIL::Design;
 
 			for (auto &it : design->modules_)
-				design_copy->modules_[it.first] = it.second->clone();
+				design_copy->add(it.second->clone());
 
 			design_copy->selection_stack = design->selection_stack;
 			design_copy->selection_vars = design->selection_vars;
@@ -242,7 +243,7 @@ struct DesignPass : public Pass {
 				pushed_designs.pop_back();
 
 			for (auto &it : saved_design->modules_)
-				design->modules_[it.first] = it.second->clone();
+				design->add(it.second->clone());
 
 			design->selection_stack = saved_design->selection_stack;
 			design->selection_vars = saved_design->selection_vars;

passes/hierarchy/hierarchy.cc

@@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules_[mod->name] = mod;
+		design->add(mod);
 
 		for (auto &decl : ports) {
 			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));

passes/hierarchy/submod.cc

@@ -105,7 +105,7 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules_[new_mod->name] = new_mod;
+		design->add(new_mod);
 		int port_counter = 1, auto_name_counter = 1;
 
 		std::set<std::string> all_wire_names;

passes/sat/miter.cc

@@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
 	RTLIL::Module *miter_module = new RTLIL::Module;
 	miter_module->name = miter_name;
-	design->modules_[miter_name] = miter_module;
+	design->add(miter_module);
 
 	RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
 	RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);

passes/techmap/extract.cc

@@ -724,7 +724,7 @@ struct ExtractPass : public Pass {
 
 				RTLIL::Module *newMod = new RTLIL::Module;
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
-				map->modules_[newMod->name] = newMod;
+				map->add(newMod);
 
 				int portCounter = 1;
 				for (auto wire : wires) {