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Added module->design and cell->module, wire->module pointers

This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions

View file

@ -477,7 +477,7 @@ struct LibertyFrontend : public Frontend {
std::string cell_name = RTLIL::escape_id(cell->args.at(0));
if (design->modules_.count(cell_name)) {
if (design->has(cell_name)) {
if (flag_ignore_redef)
continue;
log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
@ -565,7 +565,7 @@ struct LibertyFrontend : public Frontend {
}
module->fixup_ports();
design->modules_[module->name] = module;
design->add(module);
cell_count++;
skip_cell:;
}