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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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4
frontends/ilang/parser.y
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@ -90,12 +90,12 @@ design:
module:
TOK_MODULE TOK_ID EOL {
if (current_design->modules_.count($2) != 0)
if (current_design->has($2))
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
current_module = new RTLIL::Module;
current_module->name = $2;
current_module->attributes = attrbuf;
current_design->modules_[$2] = current_module;
current_design->add(current_module);
attrbuf.clear();
free($2);
} module_body TOK_END {