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Fix handling of init attributes with strange width

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This commit is contained in:
Clifford Wolf 2017-02-09 16:06:58 +01:00
parent 848062088c
commit e6cc67b46f
2 changed files with 9 additions and 3 deletions
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8
passes/opt/opt_merge.cc
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@ -280,8 +280,12 @@ struct OptMergeWorker
dff_init_map.set(module);
for (auto &it : module->wires_)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
if (it.second->attributes.count("\\init") != 0) {
Const initval = it.second->attributes.at("\\init");
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]);
}
bool did_something = true;
while (did_something)

4
passes/opt/opt_rmdff.cc
View file

@ -244,7 +244,9 @@ struct OptRmdffPass : public Pass {
{
if (wire->attributes.count("\\init") != 0) {
Const initval = wire->attributes.at("\\init");
dff_init_map.add(wire, initval);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(wire, i), initval[i]);
for (int i = 0; i < GetSize(wire); i++) {
SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit);
if (mapped_bit.wire) {