mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Fix handling of init attributes with strange width

Browse source
This commit is contained in:
Clifford Wolf 2017-02-09 16:06:58 +01:00
parent 848062088c
commit e6cc67b46f
2 changed files with 9 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/opt/opt_merge.cc
View file

@ -280,8 +280,12 @@ struct OptMergeWorker
dff_init_map.set(module);
for (auto &it : module->wires_)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
if (it.second->attributes.count("\\init") != 0) {
Const initval = it.second->attributes.at("\\init");
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]);
}
bool did_something = true;
while (did_something)