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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 08:06:57 +02:00
parent 980df499ab
commit e6ad714d20
10 changed files with 21 additions and 17 deletions
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8
tests/xilinx/mux.ys
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@ -1,8 +1,8 @@
read_verilog mux.v
design -save read
proc
hierarchy -top mux2
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D
design -load read
proc
hierarchy -top mux4
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux8
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module