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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 08:06:57 +02:00
parent 980df499ab
commit e6ad714d20
10 changed files with 21 additions and 17 deletions
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4
tests/xilinx/macc.ys
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@ -1,8 +1,8 @@
read_verilog macc.v
design -save read
proc
hierarchy -top macc
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -flatten -make_assert -make_outputs gold gate miter
@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
design -load read
proc
hierarchy -top macc2
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -flatten -make_assert -make_outputs gold gate miter