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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 08:06:57 +02:00
parent 980df499ab
commit e6ad714d20
10 changed files with 21 additions and 17 deletions
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tests/xilinx/logic.ys
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@ -1,5 +1,6 @@
read_verilog logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module