mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 13:40:53 +00:00
Code Activity

hierarchy - proc reorder

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-18 08:06:57 +02:00
parent 980df499ab
commit e6ad714d20
10 changed files with 21 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

8
tests/xilinx/adffs.ys
View file

@ -1,8 +1,8 @@
read_verilog adffs.v
design -save read
proc
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
design -load read
proc
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
design -load read
proc
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module