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Merge fb40e019aa into 5d7486115a

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Philippe Sauter 2026-06-19 05:23:00 +00:00 • committed by GitHub
commit e69890b2f0
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1 changed files with 22 additions and 4 deletions
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26
passes/opt/opt_dff.cc
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@ -55,6 +55,7 @@ struct OptDffWorker
FfInitVals initvals; FfInitVals initvals;
dict<SigBit, int> bitusers; // Signal sink count dict<SigBit, int> bitusers; // Signal sink count
dict<SigBit, cell_int_t> bit2mux; // Signal bit to driving MUX dict<SigBit, cell_int_t> bit2mux; // Signal bit to driving MUX
pool<SigBit> kept_bits;
std::vector<Cell *> dff_cells; std::vector<Cell *> dff_cells;
@ -117,15 +118,26 @@ struct OptDffWorker
// - bit2mux: the mux cell and bit index that drives it, if any // - bit2mux: the mux cell and bit index that drives it, if any
for (auto wire : module->wires()) for (auto wire : module->wires())
{
if (wire->get_bool_attribute(ID::keep))
for (auto bit : sigmap(wire))
kept_bits.insert(bit);
if (wire->port_output) if (wire->port_output)
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
bitusers[bit]++; bitusers[bit]++;
}
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++) for (int i = 0; i < GetSize(sig_y); i++) {
bit2mux[sig_y[i]] = cell_int_t(cell, i); SigBit bit = sig_y[i];
// skip kept wires, remove once yosys has optimization barriers
if (kept_bits.count(bit))
continue;
bit2mux[bit] = cell_int_t(cell, i);
}
} }
for (auto conn : cell->connections()) { for (auto conn : cell->connections()) {
@ -763,8 +775,14 @@ struct OptDffWorker
optimize_const_clk(ff, cell, changed); optimize_const_clk(ff, cell, changed);
// Feedback (D=Q) opt // Feedback (D=Q) opt
if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) {
optimize_d_equals_q(ff, cell, changed); // skip kept wires, remove once yosys has optimization barriers
bool d_has_kept_bit = false;
for (int i = 0; i < ff.width; i++)
if (kept_bits.count(ff.sig_d[i])) { d_has_kept_bit = true; break; }
if (!d_has_kept_bit)
optimize_d_equals_q(ff, cell, changed);
}
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) { if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n", log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",